1. Field of Invention
The present invention relates to a delay-locked loop. More particularly, the present invention relates to a delay locked loop detector.
2. Description of Related Art
Recently, with the outstanding improvement of the semiconductor process, the operating frequency of VLSI circuits has increased significantly. High-speed systems such as wireless phones, optical fiber links, microcomputers, and high-end system-on-a-chip (SOCs) have transmission rates at the Giga-Hertz level. Therefore, electronic devices need to upgrade their operating frequency in order to keep up with the improved semiconductor process. Furthermore, since a lot of circuits are integrated on a chip, the clock signal is entirely distributed on the chip, and clock skew problems arise as a result.
For example, when an input clock drives a chip, an uncertain delay appears between the input clock and the internal clock, which makes the chip work incorrectly. In order to synchronize the various clock signals and suppress the clock skew on the chip, the phase-locked loop (PLLs) and delay-locked loop (DLLs) have been applied in many high-speed circuits and systems.
FIG. 1 shows a block diagram of the conventional DLL. The DLL includes a voltage-controlled delay line 107 (VCDL), a phase detector 101 (PD), a loop filter 105 (LF), and a charge pump 103 (CP). The PD 101 detects the phase difference between the internal clock and the input clock. The LF 105 is usually implemented with a single capacitor, which is charged/discharged by the CP 103, to reduce high-frequency noise and provide a constant dc level to the VCDL 107.
The PD 101 output signals UP and DN are integrated into the CP 103 and LF 105 to generate a control voltage (VCTL) for the delay line 107. When the circuit is locked, VCTL is a constant and the VCDL 107 finds the optimum path so that the input clock and the internal clock can be synchronized.
However, in this conventional DLL, the irregular high supply voltage or a clock signal with many jitters might cause the VCTL to exceed the proper voltage range, and the VCTL is unable to return back to the normal voltage range, which makes the DLL deadlock at the wrong frequency, that is, the DLL cannot generate a clock signal with an expected frequency, and the whole circuit on the chip might operate at the wrong frequency as a result.
Therefore, there is a need for a new delay-locked loop and a detection circuit thereof which can tell if the DLL is deadlock at wrong frequency and rectify the situation accordingly.